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<div class="textblock"><p><a class="el" href="xilskey__epl_8c.html" title="xilskey_epl.c ">xilskey_epl.c</a> </p>
<dl class="section note"><dt>Note</dt><dd><pre class="fragment">                    Contains the function definitions for the PL eFUSE functionality.
</pre></dd></dl>
<p>MODIFICATION HISTORY:</p>
<p>Ver Who Date Changes </p>
<hr/>
<p> 1.00a rpoolla 04/26/13 First release 1.02a hk 10/28/13 Added API's to read status bits and key.PR# 735957 2.00 hk 22/01/14 Corrected PL voltage checks to VCCINT and VCCAUX. CR#768077 2.1 kvn 04/01/15 Fixed warnings. CR#716453. 3.00 vns 31/07/15 Added efuse functionality for Ultrascale. 4.0 vns 10/01/15 provided conditional compilation to support ZynqMp platform also. Corrected error code names of Ultrascale efuse PL 5.0 vns 07/01/16 Verificaion of programming bits is done by performing all Margin reads. Added conditions for programming control and secure bits. 6.00 vns 29/06/16 Added Margin 2 read verification after programming every Zynq's eFUSE PL bit CR #953052. 07/07/16 Modified XilSKey_EfusePl_ProgramBit_Ultra such that it returns error code when JtagWrite_Ultrascale fails programming eFUSE bit. Error occurs only when Hardware Module has encountered timeout. 26/07/16 Added 128 bit user key programming and reading. Provided single bit programming feature for 32 and 128 bit user keys for eFUSE Ultrascale. 6.4 vns 02/27/18 Added support for programming secure bit 6 - enable obfuscation feature for eFUSE AES key 6.6 vns 06/06/18 Added doxygen tags 6.7 psl 03/20/19 Added eFuse key write support for SSIT devices. arc 04/04/19 Fixed CPP warnings. psl 04/15/19 Added JtagServerInit function. 6.8 psl 05/21/19 Added else case to clear UserFuses_TobePrgrmd psl 08/23/19 Added Debug define to avoid writing of eFuse. vns 08/29/19 Initialized Status variables 6.9 vns 03/18/20 Fixed Armcc compilation errors 7.2 am 07/13/21 Fixed doxygen warnings 7.3 har 11/15/21 Removed local variable ErrorCode in XilSKey_EfusePl_GetRowData_Ultra()</p>
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Macros</h2></td></tr>
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<tr class="memdesc:ad9ff84e6d99e4e3bac14409dd6912c69"><td class="mdescLeft">&#160;</td><td class="mdescRight">Fuse Ctrl Row.  <a href="#ad9ff84e6d99e4e3bac14409dd6912c69">More...</a><br/></td></tr>
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<tr class="memdesc:a6c30e3653be249cb96ae7b04007993ff"><td class="mdescLeft">&#160;</td><td class="mdescRight">AES Key size.  <a href="#a6c30e3653be249cb96ae7b04007993ff">More...</a><br/></td></tr>
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<tr class="memitem:a7edd630a1c41c7c2f84afbce254374bb"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="xilskey__epl_8c.html#a7edd630a1c41c7c2f84afbce254374bb">XSK_EFUSEPL_ARRAY_FUSE_USER_KEY_SIZE</a>&#160;&#160;&#160;(32)</td></tr>
<tr class="memdesc:a7edd630a1c41c7c2f84afbce254374bb"><td class="mdescLeft">&#160;</td><td class="mdescRight">32 bit User key size  <a href="#a7edd630a1c41c7c2f84afbce254374bb">More...</a><br/></td></tr>
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<tr class="memitem:a668c1b4f2d82a98eaf65a1db86e4e02a"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="xilskey__epl_8c.html#a668c1b4f2d82a98eaf65a1db86e4e02a">XSK_EFUSEPL_ARRAY_MAX_COL</a>&#160;&#160;&#160;(32)</td></tr>
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<tr class="memitem:acc49ad5b76e54ed8c1817b21c3438b98"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="xilskey__epl_8c.html#acc49ad5b76e54ed8c1817b21c3438b98">XSK_EFUSEPL_ARRAY_FUSE_CNTRL_REDUNDENT_START_BIT</a>&#160;&#160;&#160;(14)</td></tr>
<tr class="memdesc:acc49ad5b76e54ed8c1817b21c3438b98"><td class="mdescLeft">&#160;</td><td class="mdescRight">Redundant bit start Index.  <a href="#acc49ad5b76e54ed8c1817b21c3438b98">More...</a><br/></td></tr>
<tr class="separator:acc49ad5b76e54ed8c1817b21c3438b98"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:a35bc722e37bbf9b89c3f92def4823bb8"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="xilskey__epl_8c.html#a35bc722e37bbf9b89c3f92def4823bb8">XSK_EFUSEPL_ARRAY_UNSUPPORTED_RED_FOR_BIT6</a>&#160;&#160;&#160;(20)</td></tr>
<tr class="memdesc:a35bc722e37bbf9b89c3f92def4823bb8"><td class="mdescLeft">&#160;</td><td class="mdescRight">Unsupported bit.  <a href="#a35bc722e37bbf9b89c3f92def4823bb8">More...</a><br/></td></tr>
<tr class="separator:a35bc722e37bbf9b89c3f92def4823bb8"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:a52da5afc1f49a09f9f2a7faac4fa1746"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="xilskey__epl_8c.html#a52da5afc1f49a09f9f2a7faac4fa1746">XSK_EFUSEPL_ARRAY_UNSUPPORTED_RED_FOR_BIT7</a>&#160;&#160;&#160;(21)</td></tr>
<tr class="memdesc:a52da5afc1f49a09f9f2a7faac4fa1746"><td class="mdescLeft">&#160;</td><td class="mdescRight">Unsupported bit.  <a href="#a52da5afc1f49a09f9f2a7faac4fa1746">More...</a><br/></td></tr>
<tr class="separator:a52da5afc1f49a09f9f2a7faac4fa1746"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:a655b038e7764d378fdb39efc9b6e344c"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="xilskey__epl_8c.html#a655b038e7764d378fdb39efc9b6e344c">XSK_EFUSEPL_ARRAY_FUSE_CNTRL_REDUNDENT_END_BIT</a>&#160;&#160;&#160;(24)</td></tr>
<tr class="memdesc:a655b038e7764d378fdb39efc9b6e344c"><td class="mdescLeft">&#160;</td><td class="mdescRight">Redundant bit End Index.  <a href="#a655b038e7764d378fdb39efc9b6e344c">More...</a><br/></td></tr>
<tr class="separator:a655b038e7764d378fdb39efc9b6e344c"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:a8dab4092fffc9c9ef6d80843f98ef457"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="xilskey__epl_8c.html#a8dab4092fffc9c9ef6d80843f98ef457">XSK_EFUSEPL_MAX_REF_CLK_FREQ</a>&#160;&#160;&#160;60000000</td></tr>
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<tr class="separator:a8dab4092fffc9c9ef6d80843f98ef457"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ab595634f414538c8c30052c2719f3bf4"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="xilskey__epl_8c.html#ab595634f414538c8c30052c2719f3bf4">XSK_EFUSEPL_MIN_REF_CLK_FREQ</a>&#160;&#160;&#160;20000000</td></tr>
<tr class="memdesc:ab595634f414538c8c30052c2719f3bf4"><td class="mdescLeft">&#160;</td><td class="mdescRight">Min Ref Clk Frequency.  <a href="#ab595634f414538c8c30052c2719f3bf4">More...</a><br/></td></tr>
<tr class="separator:ab595634f414538c8c30052c2719f3bf4"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ab57e87661cd1c70cdfc11764aa741ef1"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="xilskey__epl_8c.html#ab57e87661cd1c70cdfc11764aa741ef1">XSK_EFUSEPL_CNTRL_ROW_ULTRA</a>&#160;&#160;&#160;(1)</td></tr>
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<tr class="separator:ab57e87661cd1c70cdfc11764aa741ef1"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:a1db1953a12bf1e0690df83306e18cfbc"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="xilskey__epl_8c.html#a1db1953a12bf1e0690df83306e18cfbc">XSK_EFUSEPL_DNA_ROW_ULTRA</a>&#160;&#160;&#160;(7)</td></tr>
<tr class="memdesc:a1db1953a12bf1e0690df83306e18cfbc"><td class="mdescLeft">&#160;</td><td class="mdescRight">DNA row of FUSE for Ultrascale series.  <a href="#a1db1953a12bf1e0690df83306e18cfbc">More...</a><br/></td></tr>
<tr class="separator:a1db1953a12bf1e0690df83306e18cfbc"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:a6cbe0813ce06b0f5f109321ba9d9ba1d"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="xilskey__epl_8c.html#a6cbe0813ce06b0f5f109321ba9d9ba1d">XSK_EFUSEPL_AES_ROW_START_ULTRA</a>&#160;&#160;&#160;(20)</td></tr>
<tr class="memdesc:a6cbe0813ce06b0f5f109321ba9d9ba1d"><td class="mdescLeft">&#160;</td><td class="mdescRight">AES key start row of FUSE for Ultrascale series.  <a href="#a6cbe0813ce06b0f5f109321ba9d9ba1d">More...</a><br/></td></tr>
<tr class="separator:a6cbe0813ce06b0f5f109321ba9d9ba1d"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:abf99b08e9d05da21ca6433bc4373d776"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="xilskey__epl_8c.html#abf99b08e9d05da21ca6433bc4373d776">XSK_EFUSEPL_AES_ROW_END_ULTRA</a>&#160;&#160;&#160;(27)</td></tr>
<tr class="memdesc:abf99b08e9d05da21ca6433bc4373d776"><td class="mdescLeft">&#160;</td><td class="mdescRight">AES key end row of FUSE for Ultrascale series.  <a href="#abf99b08e9d05da21ca6433bc4373d776">More...</a><br/></td></tr>
<tr class="separator:abf99b08e9d05da21ca6433bc4373d776"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ab81b69f44f409d9b8ea3cae46991a784"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="xilskey__epl_8c.html#ab81b69f44f409d9b8ea3cae46991a784">XSK_EFUSEPL_USER_ROW_ULTRA</a>&#160;&#160;&#160;(28)</td></tr>
<tr class="memdesc:ab81b69f44f409d9b8ea3cae46991a784"><td class="mdescLeft">&#160;</td><td class="mdescRight">USER key start row of FUSE for Ultrascale series.  <a href="#ab81b69f44f409d9b8ea3cae46991a784">More...</a><br/></td></tr>
<tr class="separator:ab81b69f44f409d9b8ea3cae46991a784"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:aa0eea2bede212c5830e83cba4cd6ed68"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="xilskey__epl_8c.html#aa0eea2bede212c5830e83cba4cd6ed68">XSK_EFUSEPL_SEC_ROW_ULTRA</a>&#160;&#160;&#160;(10)</td></tr>
<tr class="memdesc:aa0eea2bede212c5830e83cba4cd6ed68"><td class="mdescLeft">&#160;</td><td class="mdescRight">Secure row of FUSE for Ultrascale series.  <a href="#aa0eea2bede212c5830e83cba4cd6ed68">More...</a><br/></td></tr>
<tr class="separator:aa0eea2bede212c5830e83cba4cd6ed68"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:a5cb41e0920367bf4203baaad5d3ac831"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="xilskey__epl_8c.html#a5cb41e0920367bf4203baaad5d3ac831">XSK_EFUSEPL_RSA_ROW_START_ULTRA</a>&#160;&#160;&#160;(12)</td></tr>
<tr class="memdesc:a5cb41e0920367bf4203baaad5d3ac831"><td class="mdescLeft">&#160;</td><td class="mdescRight">RSA start row of FUSE for Ultrascale series.  <a href="#a5cb41e0920367bf4203baaad5d3ac831">More...</a><br/></td></tr>
<tr class="separator:a5cb41e0920367bf4203baaad5d3ac831"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:a9701f48edeb1d8f13ad2afe1b7884a4a"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="xilskey__epl_8c.html#a9701f48edeb1d8f13ad2afe1b7884a4a">XSK_EFUSEPL_RSA_ROW_END_ULTRA</a>&#160;&#160;&#160;(23)</td></tr>
<tr class="memdesc:a9701f48edeb1d8f13ad2afe1b7884a4a"><td class="mdescLeft">&#160;</td><td class="mdescRight">RSA end row of FUSE for Ultrascale series.  <a href="#a9701f48edeb1d8f13ad2afe1b7884a4a">More...</a><br/></td></tr>
<tr class="separator:a9701f48edeb1d8f13ad2afe1b7884a4a"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:a45b5de44e94a45932de0f0d958fc668a"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="xilskey__epl_8c.html#a45b5de44e94a45932de0f0d958fc668a">XSK_EFUSEPL_USER_128BIT_ROW_START_ULTRA</a>&#160;&#160;&#160;(0)</td></tr>
<tr class="memdesc:a45b5de44e94a45932de0f0d958fc668a"><td class="mdescLeft">&#160;</td><td class="mdescRight">128 bit USER key start row of FUSE for Ultrascale series  <a href="#a45b5de44e94a45932de0f0d958fc668a">More...</a><br/></td></tr>
<tr class="separator:a45b5de44e94a45932de0f0d958fc668a"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:a301acab7bc3bd402dde525139913ea58"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="xilskey__epl_8c.html#a301acab7bc3bd402dde525139913ea58">XSK_EFUSEPL_USER_128BIT_ROW_END_ULTRA</a>&#160;&#160;&#160;(3)</td></tr>
<tr class="memdesc:a301acab7bc3bd402dde525139913ea58"><td class="mdescLeft">&#160;</td><td class="mdescRight">128 bit USER key end row of FUSE for Ultrascale series  <a href="#a301acab7bc3bd402dde525139913ea58">More...</a><br/></td></tr>
<tr class="separator:a301acab7bc3bd402dde525139913ea58"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:a54f3f565380021d2942a1e690420cd78"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="xilskey__epl_8c.html#a54f3f565380021d2942a1e690420cd78">XSK_EFUSEPL_DNA_KEY_SIZE_ULTRA</a>&#160;&#160;&#160;(96)</td></tr>
<tr class="memdesc:a54f3f565380021d2942a1e690420cd78"><td class="mdescLeft">&#160;</td><td class="mdescRight">DNA key size of Ultrascale series.  <a href="#a54f3f565380021d2942a1e690420cd78">More...</a><br/></td></tr>
<tr class="separator:a54f3f565380021d2942a1e690420cd78"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:a73b84216f2b538ec2e08411108d2b555"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="xilskey__epl_8c.html#a73b84216f2b538ec2e08411108d2b555">XSK_EFUSEPL_RSA_HASH_SIZE_ULTRA</a>&#160;&#160;&#160;(384)</td></tr>
<tr class="memdesc:a73b84216f2b538ec2e08411108d2b555"><td class="mdescLeft">&#160;</td><td class="mdescRight">RSA hash size of Ultrascale series.  <a href="#a73b84216f2b538ec2e08411108d2b555">More...</a><br/></td></tr>
<tr class="separator:a73b84216f2b538ec2e08411108d2b555"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:a24936d81214b465d69ad46ed94c663ec"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="xilskey__epl_8c.html#a24936d81214b465d69ad46ed94c663ec">XSK_EFUSEPL_SEC_MAX_BITS_ULTRA</a>&#160;&#160;&#160;(7)</td></tr>
<tr class="memdesc:a24936d81214b465d69ad46ed94c663ec"><td class="mdescLeft">&#160;</td><td class="mdescRight">Secure row max bits of Ultrascale series.  <a href="#a24936d81214b465d69ad46ed94c663ec">More...</a><br/></td></tr>
<tr class="separator:a24936d81214b465d69ad46ed94c663ec"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:a6117759030cf75eaefaaf08523343290"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="xilskey__epl_8c.html#a6117759030cf75eaefaaf08523343290">XSK_EFUSEPL_CNTRL_MAX_BITS_ULTRA</a>&#160;&#160;&#160;(17)</td></tr>
<tr class="memdesc:a6117759030cf75eaefaaf08523343290"><td class="mdescLeft">&#160;</td><td class="mdescRight">Fuse Control max bits of Ultrascale series.  <a href="#a6117759030cf75eaefaaf08523343290">More...</a><br/></td></tr>
<tr class="separator:a6117759030cf75eaefaaf08523343290"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:a36c79b15c321dade60032001215f949d"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="xilskey__epl_8c.html#a36c79b15c321dade60032001215f949d">XSK_EFUSEPL_MAX_BITS_IN_A_ROW_ULTRA</a>&#160;&#160;&#160;(32)</td></tr>
<tr class="memdesc:a36c79b15c321dade60032001215f949d"><td class="mdescLeft">&#160;</td><td class="mdescRight">Max Pay load in Row.  <a href="#a36c79b15c321dade60032001215f949d">More...</a><br/></td></tr>
<tr class="separator:a36c79b15c321dade60032001215f949d"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ab744c4486807f8f5fc9ff5d85152ff6a"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="xilskey__epl_8c.html#ab744c4486807f8f5fc9ff5d85152ff6a">XSK_EFUSEPL_END_BIT_IN_A_ROW_ULTRA</a>&#160;&#160;&#160;(31)</td></tr>
<tr class="memdesc:ab744c4486807f8f5fc9ff5d85152ff6a"><td class="mdescLeft">&#160;</td><td class="mdescRight">FUSE end bit in a row of Ultrascale series.  <a href="#ab744c4486807f8f5fc9ff5d85152ff6a">More...</a><br/></td></tr>
<tr class="separator:ab744c4486807f8f5fc9ff5d85152ff6a"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:a7a3dfa1dc75df17382769bc43392dc3e"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="xilskey__epl_8c.html#a7a3dfa1dc75df17382769bc43392dc3e">XSK_EFUSEPL_CTRL_ROW_END_BIT_ULTRA</a>&#160;&#160;&#160;(16)</td></tr>
<tr class="memdesc:a7a3dfa1dc75df17382769bc43392dc3e"><td class="mdescLeft">&#160;</td><td class="mdescRight">Control row end bit of Ultrascale series.  <a href="#a7a3dfa1dc75df17382769bc43392dc3e">More...</a><br/></td></tr>
<tr class="separator:a7a3dfa1dc75df17382769bc43392dc3e"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:a5575a15d9850c63df2e6b611916ef242"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="xilskey__epl_8c.html#a5575a15d9850c63df2e6b611916ef242">XSK_EFUSEPL_SEC_ROW_END_BIT_ULTRA</a>&#160;&#160;&#160;(6)</td></tr>
<tr class="memdesc:a5575a15d9850c63df2e6b611916ef242"><td class="mdescLeft">&#160;</td><td class="mdescRight">Secure row end bit of Ultrascale series.  <a href="#a5575a15d9850c63df2e6b611916ef242">More...</a><br/></td></tr>
<tr class="separator:a5575a15d9850c63df2e6b611916ef242"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:a7d46ae55e8a8445adb7d03fcd271f34d"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="xilskey__epl_8c.html#a7d46ae55e8a8445adb7d03fcd271f34d">XSK_EFUSEPL_CNTRL_ROW_START_ULTRA_PLUS</a>&#160;&#160;&#160;(2)</td></tr>
<tr class="memdesc:a7d46ae55e8a8445adb7d03fcd271f34d"><td class="mdescLeft">&#160;</td><td class="mdescRight">Control row of FUSE for Ultrascale plus series.  <a href="#a7d46ae55e8a8445adb7d03fcd271f34d">More...</a><br/></td></tr>
<tr class="separator:a7d46ae55e8a8445adb7d03fcd271f34d"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:a080554ab1580195d3bacbb36651a5906"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="xilskey__epl_8c.html#a080554ab1580195d3bacbb36651a5906">XSK_EFUSEPL_CNTRL_ROW_END_ULTRA_PLUS</a>&#160;&#160;&#160;(3)</td></tr>
<tr class="memdesc:a080554ab1580195d3bacbb36651a5906"><td class="mdescLeft">&#160;</td><td class="mdescRight">Control row of FUSE for Ultrascale plus series.  <a href="#a080554ab1580195d3bacbb36651a5906">More...</a><br/></td></tr>
<tr class="separator:a080554ab1580195d3bacbb36651a5906"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:aa87ad616f07a06341e160e33727c695b"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="xilskey__epl_8c.html#aa87ad616f07a06341e160e33727c695b">XSK_EFUSEPL_DNA_ROW_START_ULTRA_PLUS</a>&#160;&#160;&#160;(0)</td></tr>
<tr class="memdesc:aa87ad616f07a06341e160e33727c695b"><td class="mdescLeft">&#160;</td><td class="mdescRight">DNA row of FUSE for Ultrascale plus series.  <a href="#aa87ad616f07a06341e160e33727c695b">More...</a><br/></td></tr>
<tr class="separator:aa87ad616f07a06341e160e33727c695b"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:a983af8e67d61c9741c53beeecac61faa"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="xilskey__epl_8c.html#a983af8e67d61c9741c53beeecac61faa">XSK_EFUSEPL_DNA_ROW_END_ULTRA_PLUS</a>&#160;&#160;&#160;(5)</td></tr>
<tr class="memdesc:a983af8e67d61c9741c53beeecac61faa"><td class="mdescLeft">&#160;</td><td class="mdescRight">DNA row of FUSE for Ultrascale plus series.  <a href="#a983af8e67d61c9741c53beeecac61faa">More...</a><br/></td></tr>
<tr class="separator:a983af8e67d61c9741c53beeecac61faa"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ad4da327de6c39915bf0bbe96673786b5"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="xilskey__epl_8c.html#ad4da327de6c39915bf0bbe96673786b5">XSK_EFUSEPL_AES_ROW_START_ULTRA_PLUS</a>&#160;&#160;&#160;(5)</td></tr>
<tr class="memdesc:ad4da327de6c39915bf0bbe96673786b5"><td class="mdescLeft">&#160;</td><td class="mdescRight">AES key start row of FUSE for Ultrascale plus series.  <a href="#ad4da327de6c39915bf0bbe96673786b5">More...</a><br/></td></tr>
<tr class="separator:ad4da327de6c39915bf0bbe96673786b5"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:a4172b30afa58ba04a33d98520b492d5a"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="xilskey__epl_8c.html#a4172b30afa58ba04a33d98520b492d5a">XSK_EFUSEPL_AES_ROW_END_ULTRA_PLUS</a>&#160;&#160;&#160;(20)</td></tr>
<tr class="memdesc:a4172b30afa58ba04a33d98520b492d5a"><td class="mdescLeft">&#160;</td><td class="mdescRight">AES key end row of FUSE for Ultrascale series.  <a href="#a4172b30afa58ba04a33d98520b492d5a">More...</a><br/></td></tr>
<tr class="separator:a4172b30afa58ba04a33d98520b492d5a"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:afcaada162bdd5661a7338a059de68af0"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="xilskey__epl_8c.html#afcaada162bdd5661a7338a059de68af0">XSK_EFUSEPL_USER_ROW_START_ULTRA_PLUS</a>&#160;&#160;&#160;(30)</td></tr>
<tr class="memdesc:afcaada162bdd5661a7338a059de68af0"><td class="mdescLeft">&#160;</td><td class="mdescRight">USER key start row of FUSE for Ultrascale plus series.  <a href="#afcaada162bdd5661a7338a059de68af0">More...</a><br/></td></tr>
<tr class="separator:afcaada162bdd5661a7338a059de68af0"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:a8a7c1770654fbe08d533f6b9496d015a"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="xilskey__epl_8c.html#a8a7c1770654fbe08d533f6b9496d015a">XSK_EFUSEPL_USER_ROW_END_ULTRA_PLUS</a>&#160;&#160;&#160;(31)</td></tr>
<tr class="memdesc:a8a7c1770654fbe08d533f6b9496d015a"><td class="mdescLeft">&#160;</td><td class="mdescRight">USER key start row of FUSE for Ultrascale plus series.  <a href="#a8a7c1770654fbe08d533f6b9496d015a">More...</a><br/></td></tr>
<tr class="separator:a8a7c1770654fbe08d533f6b9496d015a"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:a4028e62af94e327b59fe19e88d50954a"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="xilskey__epl_8c.html#a4028e62af94e327b59fe19e88d50954a">XSK_EFUSEPL_SEC_ROW_ULTRA_PLUS</a>&#160;&#160;&#160;(4)</td></tr>
<tr class="memdesc:a4028e62af94e327b59fe19e88d50954a"><td class="mdescLeft">&#160;</td><td class="mdescRight">Secure row of FUSE for Ultrascale series.  <a href="#a4028e62af94e327b59fe19e88d50954a">More...</a><br/></td></tr>
<tr class="separator:a4028e62af94e327b59fe19e88d50954a"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:a10fa4c8974224924541dbd93f1116c0f"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="xilskey__epl_8c.html#a10fa4c8974224924541dbd93f1116c0f">XSK_EFUSEPL_RSA_ROW_START_ULTRA_PLUS</a>&#160;&#160;&#160;(6)</td></tr>
<tr class="memdesc:a10fa4c8974224924541dbd93f1116c0f"><td class="mdescLeft">&#160;</td><td class="mdescRight">RSA start row of FUSE for Ultrascale plus series.  <a href="#a10fa4c8974224924541dbd93f1116c0f">More...</a><br/></td></tr>
<tr class="separator:a10fa4c8974224924541dbd93f1116c0f"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:aa69b916adceb1705aaa056e34cb3b853"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="xilskey__epl_8c.html#aa69b916adceb1705aaa056e34cb3b853">XSK_EFUSEPL_RSA_ROW_END_ULTRA_PLUS</a>&#160;&#160;&#160;(29)</td></tr>
<tr class="memdesc:aa69b916adceb1705aaa056e34cb3b853"><td class="mdescLeft">&#160;</td><td class="mdescRight">RSA end row of FUSE for Ultrascale plus series.  <a href="#aa69b916adceb1705aaa056e34cb3b853">More...</a><br/></td></tr>
<tr class="separator:aa69b916adceb1705aaa056e34cb3b853"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:a08c0decf4b0fff61451eb2b694e1af29"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="xilskey__epl_8c.html#a08c0decf4b0fff61451eb2b694e1af29">XSK_EFUSEPL_USER_128BIT_ROW_START_ULTRA_PLUS</a>&#160;&#160;&#160;(21)</td></tr>
<tr class="memdesc:a08c0decf4b0fff61451eb2b694e1af29"><td class="mdescLeft">&#160;</td><td class="mdescRight">128 bit USER key start row of FUSE for Ultrascale plus series  <a href="#a08c0decf4b0fff61451eb2b694e1af29">More...</a><br/></td></tr>
<tr class="separator:a08c0decf4b0fff61451eb2b694e1af29"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:a720c60fbb27fbc6a4da2250b46cadd42"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="xilskey__epl_8c.html#a720c60fbb27fbc6a4da2250b46cadd42">XSK_EFUSEPL_USER_128BIT_ROW_END_ULTRA_PLUS</a>&#160;&#160;&#160;(28)</td></tr>
<tr class="memdesc:a720c60fbb27fbc6a4da2250b46cadd42"><td class="mdescLeft">&#160;</td><td class="mdescRight">128 bit USER key end row of FUSE for Ultrascale plus series  <a href="#a720c60fbb27fbc6a4da2250b46cadd42">More...</a><br/></td></tr>
<tr class="separator:a720c60fbb27fbc6a4da2250b46cadd42"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:a45aabab52e0458600e145ccbfa1404a2"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="xilskey__epl_8c.html#a45aabab52e0458600e145ccbfa1404a2">XSK_EFUSEPL_CTRL_ROW_UNSUPPORT_BIT3_ULTRA</a>&#160;&#160;&#160;(3)</td></tr>
<tr class="memdesc:a45aabab52e0458600e145ccbfa1404a2"><td class="mdescLeft">&#160;</td><td class="mdescRight">Unsupported bits of Control register.  <a href="#a45aabab52e0458600e145ccbfa1404a2">More...</a><br/></td></tr>
<tr class="separator:a45aabab52e0458600e145ccbfa1404a2"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:a0addc2b729efcd07c5e8321ce42bf079"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="xilskey__epl_8c.html#a0addc2b729efcd07c5e8321ce42bf079">XSK_EFUSEPL_CTRL_ROW_UNSUPPORT_BIT4_ULTRA</a>&#160;&#160;&#160;(4)</td></tr>
<tr class="memdesc:a0addc2b729efcd07c5e8321ce42bf079"><td class="mdescLeft">&#160;</td><td class="mdescRight">&lt; Unsupported bit in ctrl register  <a href="#a0addc2b729efcd07c5e8321ce42bf079">More...</a><br/></td></tr>
<tr class="separator:a0addc2b729efcd07c5e8321ce42bf079"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:a5b7d16d963896034d14f97703d25c9f6"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="xilskey__epl_8c.html#a5b7d16d963896034d14f97703d25c9f6">XSK_EFUSEPL_CTRL_ROW_UNSUPPORT_BIT_RANGE_START_ULTRA</a>&#160;&#160;&#160;(10)</td></tr>
<tr class="memdesc:a5b7d16d963896034d14f97703d25c9f6"><td class="mdescLeft">&#160;</td><td class="mdescRight">&lt; Unsupported bit in ctrl register  <a href="#a5b7d16d963896034d14f97703d25c9f6">More...</a><br/></td></tr>
<tr class="separator:a5b7d16d963896034d14f97703d25c9f6"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ae27dbc5b15b3c278543e67efddf6f898"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="xilskey__epl_8c.html#ae27dbc5b15b3c278543e67efddf6f898">XSK_EFUSEPL_CTRL_ROW_UNSUPPORT_BIT_RANGE_END_ULTRA</a>&#160;&#160;&#160;(14)</td></tr>
<tr class="memdesc:ae27dbc5b15b3c278543e67efddf6f898"><td class="mdescLeft">&#160;</td><td class="mdescRight">&lt; Unsupported bit in ctrl register  <a href="#ae27dbc5b15b3c278543e67efddf6f898">More...</a><br/></td></tr>
<tr class="separator:ae27dbc5b15b3c278543e67efddf6f898"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:a8dab4092fffc9c9ef6d80843f98ef457"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="xilskey__epl_8c.html#a8dab4092fffc9c9ef6d80843f98ef457">XSK_EFUSEPL_MAX_REF_CLK_FREQ</a>&#160;&#160;&#160;60000000</td></tr>
<tr class="memdesc:a8dab4092fffc9c9ef6d80843f98ef457"><td class="mdescLeft">&#160;</td><td class="mdescRight">Max Ref Clk Frequency.  <a href="#a8dab4092fffc9c9ef6d80843f98ef457">More...</a><br/></td></tr>
<tr class="separator:a8dab4092fffc9c9ef6d80843f98ef457"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ab595634f414538c8c30052c2719f3bf4"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="xilskey__epl_8c.html#ab595634f414538c8c30052c2719f3bf4">XSK_EFUSEPL_MIN_REF_CLK_FREQ</a>&#160;&#160;&#160;20000000</td></tr>
<tr class="memdesc:ab595634f414538c8c30052c2719f3bf4"><td class="mdescLeft">&#160;</td><td class="mdescRight">Min Ref Clk Frequency.  <a href="#ab595634f414538c8c30052c2719f3bf4">More...</a><br/></td></tr>
<tr class="separator:ab595634f414538c8c30052c2719f3bf4"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:a8d3288d93ff8fbb642c62fda2318014f"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="xilskey__epl_8c.html#a8d3288d93ff8fbb642c62fda2318014f">XSK_EFUSEPL_PAGE_0_ULTRA</a>&#160;&#160;&#160;(0)</td></tr>
<tr class="memdesc:a8d3288d93ff8fbb642c62fda2318014f"><td class="mdescLeft">&#160;</td><td class="mdescRight">Page 0 for Ultrascale series.  <a href="#a8d3288d93ff8fbb642c62fda2318014f">More...</a><br/></td></tr>
<tr class="separator:a8d3288d93ff8fbb642c62fda2318014f"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:a33e4b4e324f30f256e29d644bf16f840"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="xilskey__epl_8c.html#a33e4b4e324f30f256e29d644bf16f840">XSK_EFUSEPL_PAGE_1_ULTRA</a>&#160;&#160;&#160;(1)</td></tr>
<tr class="memdesc:a33e4b4e324f30f256e29d644bf16f840"><td class="mdescLeft">&#160;</td><td class="mdescRight">Page 1 for Ultrascale series.  <a href="#a33e4b4e324f30f256e29d644bf16f840">More...</a><br/></td></tr>
<tr class="separator:a33e4b4e324f30f256e29d644bf16f840"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:a12be050ae2a88b04c6a5401dd9c1f4b7"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="xilskey__epl_8c.html#a12be050ae2a88b04c6a5401dd9c1f4b7">XSK_EFUSEPL_REDUNDANT_ULTRA</a>&#160;&#160;&#160;(1)</td></tr>
<tr class="memdesc:a12be050ae2a88b04c6a5401dd9c1f4b7"><td class="mdescLeft">&#160;</td><td class="mdescRight">Redundant read selection for Ultrascale series.  <a href="#a12be050ae2a88b04c6a5401dd9c1f4b7">More...</a><br/></td></tr>
<tr class="separator:a12be050ae2a88b04c6a5401dd9c1f4b7"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:a5c55c664fa9ebd10dffae1f6af853239"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="xilskey__epl_8c.html#a5c55c664fa9ebd10dffae1f6af853239">XSK_EFUSEPL_NORMAL_ULTRA</a>&#160;&#160;&#160;(0)</td></tr>
<tr class="memdesc:a5c55c664fa9ebd10dffae1f6af853239"><td class="mdescLeft">&#160;</td><td class="mdescRight">Normal read selection for Ultrascale series.  <a href="#a5c55c664fa9ebd10dffae1f6af853239">More...</a><br/></td></tr>
<tr class="separator:a5c55c664fa9ebd10dffae1f6af853239"><td class="memSeparator" colspan="2">&#160;</td></tr>
</table><table class="memberdecls">
<tr class="heading"><td colspan="2"><h2 class="groupheader"><a name="enum-members"></a>
Enumerations</h2></td></tr>
<tr class="memitem:a4f87dd891cf4f17bd68a9820622917d5"><td class="memItemLeft" align="right" valign="top">enum &#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="xilskey__epl_8c.html#a4f87dd891cf4f17bd68a9820622917d5">XSK_EfusePl_MarginOption</a> { <a class="el" href="xilskey__epl_8c.html#a4f87dd891cf4f17bd68a9820622917d5aff7202698f203b2ec237193f55537b0c">XSK_EFUSEPL_READ_NORMAL</a> = 0x1,
<a class="el" href="xilskey__epl_8c.html#a4f87dd891cf4f17bd68a9820622917d5a6d4355c10eef92db810e21fb8a987c91">XSK_EFUSEPL_READ_MARGIN_1</a> = 0x2,
<a class="el" href="xilskey__epl_8c.html#a4f87dd891cf4f17bd68a9820622917d5a264bbce97fef27d2300c0bb4e4080329">XSK_EFUSEPL_READ_MARGIN_2</a> = 0x4,
<a class="el" href="xilskey__epl_8c.html#a4f87dd891cf4f17bd68a9820622917d5aef053ed40f210a230d2efd471ef3a5df">XSK_EFUSEPL_READ_MARGIN_MAX</a> = 0x7
 }</td></tr>
<tr class="memdesc:a4f87dd891cf4f17bd68a9820622917d5"><td class="mdescLeft">&#160;</td><td class="mdescRight">Read or Write eFUSE Margin Options.  <a href="xilskey__epl_8c.html#a4f87dd891cf4f17bd68a9820622917d5">More...</a><br/></td></tr>
<tr class="separator:a4f87dd891cf4f17bd68a9820622917d5"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ad788ed0003b0c5dcb8b56ad9c34961de"><td class="memItemLeft" align="right" valign="top">enum &#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="xilskey__epl_8c.html#ad788ed0003b0c5dcb8b56ad9c34961de">XSKEfusePl_FuseCntrlBits</a> { <br/>
&#160;&#160;<a class="el" href="xilskey__epl_8c.html#ad788ed0003b0c5dcb8b56ad9c34961dea564ab9c065e6fe01852339b6a334d1ab">XSK_EFUSEPL_CNTRL_FORCE_PCYCLE_RECONFIG</a> = 0x01,
<a class="el" href="xilskey__epl_8c.html#ad788ed0003b0c5dcb8b56ad9c34961dea2d2072c692c5f90cdde64e7297f0cb5c">XSK_EFUSEPL_CNTRL_DISABLE_KEY_WRITE</a>,
<a class="el" href="xilskey__epl_8c.html#ad788ed0003b0c5dcb8b56ad9c34961dea9654c58aff7a6ddc2c4cf85ba520cfe5">XSK_EFUSEPL_CNTRL_DISABLE_AES_KEY_READ</a>,
<a class="el" href="xilskey__epl_8c.html#ad788ed0003b0c5dcb8b56ad9c34961deacc5ba1a4a66dffce7060cabece3036a7">XSK_EFUSEPL_CNTRL_DISABLE_USER_KEY_READ</a>,
<br/>
&#160;&#160;<a class="el" href="xilskey__epl_8c.html#ad788ed0003b0c5dcb8b56ad9c34961deab750d0e7bad9ce3b945cae613e1a8148">XSK_EFUSEPL_CNTRL_DISABLE_FUSE_CNTRL_WRITE</a>,
<a class="el" href="xilskey__epl_8c.html#ad788ed0003b0c5dcb8b56ad9c34961dea25c43fe81e29a37602dc86038feb0d12">XSK_EFUSEPL_CNTRL_FORCE_USE_AES_ONLY</a> = 0x08,
<a class="el" href="xilskey__epl_8c.html#ad788ed0003b0c5dcb8b56ad9c34961dea0b45e58b49a9ce025978d2fa3f0584d0">XSK_EFUSEPL_CNTRL_JTAG_CHAIN_DISABLE</a>,
<a class="el" href="xilskey__epl_8c.html#ad788ed0003b0c5dcb8b56ad9c34961deaf165e629ce040fd70086730f877890a9">XSK_EFUSEPL_CNTRL_BBRAM_KEY_DISABLE</a>
<br/>
 }</td></tr>
<tr class="memdesc:ad788ed0003b0c5dcb8b56ad9c34961de"><td class="mdescLeft">&#160;</td><td class="mdescRight">Fuse Control Row Bit Indices.  <a href="xilskey__epl_8c.html#ad788ed0003b0c5dcb8b56ad9c34961de">More...</a><br/></td></tr>
<tr class="separator:ad788ed0003b0c5dcb8b56ad9c34961de"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ac9a38d78264d1de965de9ea375b7486f"><td class="memItemLeft" align="right" valign="top">enum &#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="xilskey__epl_8c.html#ac9a38d78264d1de965de9ea375b7486f">XSKEfusePl_FuseCntrlBits_Ultra</a> { <br/>
&#160;&#160;<a class="el" href="xilskey__epl_8c.html#ac9a38d78264d1de965de9ea375b7486fa9f12db83dcd56d735b3d3db595eb5bbb">XSK_EFUSEPL_CNTRL_DISABLE_KEY_RD_ULTRA</a>,
<a class="el" href="xilskey__epl_8c.html#ac9a38d78264d1de965de9ea375b7486faccd7ea296b35f2b1edeb6cdd32645d8f">XSK_EFUSEPL_CNTRL_DISABLE_USER_KEY_RD_ULTRA</a>,
<a class="el" href="xilskey__epl_8c.html#ac9a38d78264d1de965de9ea375b7486faf8ade165a1c788079deb288b3bcf906a">XSK_EFUSEPL_CNTRL_DISABLE_SEC_RD_ULTRA</a>,
<a class="el" href="xilskey__epl_8c.html#ac9a38d78264d1de965de9ea375b7486fa2c25d3a65e34751ebd2ec70c6949f7c1">XSK_EFUSEPL_CNTRL_DISABLE_CNTRL_WR_ULTRA</a> = 5,
<br/>
&#160;&#160;<a class="el" href="xilskey__epl_8c.html#ac9a38d78264d1de965de9ea375b7486faf17bb1f794362faa4a0d1e6e67d2dceb">XSK_EFUSEPL_CNTRL_DISABLE_RSA_KEY_RD_ULTRA</a>,
<a class="el" href="xilskey__epl_8c.html#ac9a38d78264d1de965de9ea375b7486faca83d34b380088bbc30592632bf7a935">XSK_EFUSEPL_CNTRL_DISABLE_KEY_WR_ULTRA</a>,
<a class="el" href="xilskey__epl_8c.html#ac9a38d78264d1de965de9ea375b7486fa681b7a86d2cb18443929764e200608bd">XSK_EFUSEPL_CNTRL_DISABLE_USER_KEY_WR_ULTRA</a>,
<a class="el" href="xilskey__epl_8c.html#ac9a38d78264d1de965de9ea375b7486fa2c60152852ba70d49741c4364e542596">XSK_EFUSEPL_CNTRL_DISABLE_SEC_WR_ULTRA</a>,
<br/>
&#160;&#160;<a class="el" href="xilskey__epl_8c.html#ac9a38d78264d1de965de9ea375b7486fa8bde903764407a85423d4f01082d4961">XSK_EFUSEPL_CNTRL_DISABLE_RSA_KEY_WR_ULTRA</a> = 15,
<a class="el" href="xilskey__epl_8c.html#ac9a38d78264d1de965de9ea375b7486fa5f3b141d98f753bae39ea1924ae35bc5">XSK_EFUSEPL_CNTRL_DISABLE_128BIT_USR_KEY_WR_ULTRA</a>
<br/>
 }</td></tr>
<tr class="memdesc:ac9a38d78264d1de965de9ea375b7486f"><td class="mdescLeft">&#160;</td><td class="mdescRight">Fuse Control Row Bit Indices of Ultrascale series.  <a href="xilskey__epl_8c.html#ac9a38d78264d1de965de9ea375b7486f">More...</a><br/></td></tr>
<tr class="separator:ac9a38d78264d1de965de9ea375b7486f"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ac9b6d5e426c9bbc6af1138801bf8e1ca"><td class="memItemLeft" align="right" valign="top">enum &#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="xilskey__epl_8c.html#ac9b6d5e426c9bbc6af1138801bf8e1ca">XSKEfusePl_FuseSecureBits_Ultra</a> { <br/>
&#160;&#160;<a class="el" href="xilskey__epl_8c.html#ac9b6d5e426c9bbc6af1138801bf8e1caa1f950d11fb2fd1f1acbf7fe7a0a02176">XSK_EFUSEPL_SEC_ALLOW_ENCRYPT_ONLY</a>,
<a class="el" href="xilskey__epl_8c.html#ac9b6d5e426c9bbc6af1138801bf8e1caa2cddeeb70f3e8f6b0f94b46f138ccd6e">XSK_EFUSEPL_SEC_FORCE_AES_ONLY_ULTRA</a>,
<a class="el" href="xilskey__epl_8c.html#ac9b6d5e426c9bbc6af1138801bf8e1caad65d494b7924ac982cb826c4213fa858">XSK_EFUSEPL_SEC_RSA_AUTH_EN_ULTRA</a>,
<a class="el" href="xilskey__epl_8c.html#ac9b6d5e426c9bbc6af1138801bf8e1caa14662984cc3828fcb3ba223d4f104a97">XSK_EFUSEPL_SEC_JTAG_CHAIN_DISABLE_ULTRA</a>,
<br/>
&#160;&#160;<a class="el" href="xilskey__epl_8c.html#ac9b6d5e426c9bbc6af1138801bf8e1caacc2d06b97690397fc05fc49992045666">XSK_EFUSEPL_SEC_DISABLE_INTRNL_TEST_ACCESS_ULTRA</a>,
<a class="el" href="xilskey__epl_8c.html#ac9b6d5e426c9bbc6af1138801bf8e1caad875450d5ae299147ca224c51326c2ae">XSK_EFUSEPL_SEC_DISABLE_DECRPTR_ULTRA</a>,
<a class="el" href="xilskey__epl_8c.html#ac9b6d5e426c9bbc6af1138801bf8e1caad23d8f5886a446c350c4c821e008c09c">XSK_EFUSEPL_SEC_ENABLE_OBFUSCATION_ULTRA</a>
<br/>
 }</td></tr>
<tr class="memdesc:ac9b6d5e426c9bbc6af1138801bf8e1ca"><td class="mdescLeft">&#160;</td><td class="mdescRight">Fuse Secure Row Bit Indices of Ultrascale series.  <a href="xilskey__epl_8c.html#ac9b6d5e426c9bbc6af1138801bf8e1ca">More...</a><br/></td></tr>
<tr class="separator:ac9b6d5e426c9bbc6af1138801bf8e1ca"><td class="memSeparator" colspan="2">&#160;</td></tr>
</table><table class="memberdecls">
<tr class="heading"><td colspan="2"><h2 class="groupheader"><a name="func-members"></a>
Functions</h2></td></tr>
<tr class="memitem:a679f7e8d71ad7dc330c2ace859a3d20a"><td class="memItemLeft" align="right" valign="top">int&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="xilskey__epl_8c.html#a679f7e8d71ad7dc330c2ace859a3d20a">JtagServerInit</a> (<a class="el" href="struct_xil_s_key___e_pl.html">XilSKey_EPl</a> *PlInstancePtr)</td></tr>
<tr class="memdesc:a679f7e8d71ad7dc330c2ace859a3d20a"><td class="mdescLeft">&#160;</td><td class="mdescRight">JTAG Server Initialization routine.  <a href="#a679f7e8d71ad7dc330c2ace859a3d20a">More...</a><br/></td></tr>
<tr class="separator:a679f7e8d71ad7dc330c2ace859a3d20a"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:a8a1a649f81c76f0a81196ac2d6a411bc"><td class="memItemLeft" align="right" valign="top">void&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="xilskey__epl_8c.html#a8a1a649f81c76f0a81196ac2d6a411bc">JtagWrite</a> (unsigned char row, unsigned char bit)</td></tr>
<tr class="memdesc:a8a1a649f81c76f0a81196ac2d6a411bc"><td class="mdescLeft">&#160;</td><td class="mdescRight">JTAG Server Write routine.  <a href="#a8a1a649f81c76f0a81196ac2d6a411bc">More...</a><br/></td></tr>
<tr class="separator:a8a1a649f81c76f0a81196ac2d6a411bc"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:a59fd1f16ea68cca3d04d37883079e6f4"><td class="memItemLeft" align="right" valign="top">void&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="xilskey__epl_8c.html#a59fd1f16ea68cca3d04d37883079e6f4">JtagRead</a> (unsigned char row, unsigned int *row_data, unsigned char marginOption)</td></tr>
<tr class="memdesc:a59fd1f16ea68cca3d04d37883079e6f4"><td class="mdescLeft">&#160;</td><td class="mdescRight">JTAG Server Read routine.  <a href="#a59fd1f16ea68cca3d04d37883079e6f4">More...</a><br/></td></tr>
<tr class="separator:a59fd1f16ea68cca3d04d37883079e6f4"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ad71fe773dff0bd882d39c2936e319c63"><td class="memItemLeft" align="right" valign="top">int&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="xilskey__epl_8c.html#ad71fe773dff0bd882d39c2936e319c63">JtagWrite_Ultrascale</a> (u8 Row, u8 Bit, u8 Page, u8 Redundant)</td></tr>
<tr class="memdesc:ad71fe773dff0bd882d39c2936e319c63"><td class="mdescLeft">&#160;</td><td class="mdescRight">This function blows the fuse of Ultrascale with provided parameters.  <a href="#ad71fe773dff0bd882d39c2936e319c63">More...</a><br/></td></tr>
<tr class="separator:ad71fe773dff0bd882d39c2936e319c63"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:a2740a0531078952f78e0b2680f62cd1a"><td class="memItemLeft" align="right" valign="top">void&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="xilskey__epl_8c.html#a2740a0531078952f78e0b2680f62cd1a">JtagRead_Ultrascale</a> (u8 Row, u32 *RowData, u8 MarginOption, u8 Page, u8 Redundant)</td></tr>
<tr class="memdesc:a2740a0531078952f78e0b2680f62cd1a"><td class="mdescLeft">&#160;</td><td class="mdescRight">This function reads entire row of Ultrascale's EFUSE.  <a href="#a2740a0531078952f78e0b2680f62cd1a">More...</a><br/></td></tr>
<tr class="separator:a2740a0531078952f78e0b2680f62cd1a"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:a81be870dc9cfe995815d14bc106473a7"><td class="memItemLeft" align="right" valign="top">void&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="xilskey__epl_8c.html#a81be870dc9cfe995815d14bc106473a7">JtagRead_Status_Ultrascale</a> (u32 *Rowdata)</td></tr>
<tr class="memdesc:a81be870dc9cfe995815d14bc106473a7"><td class="mdescLeft">&#160;</td><td class="mdescRight">This function reads the status row of Ultrascale's EFUSE and updates the pointer.  <a href="#a81be870dc9cfe995815d14bc106473a7">More...</a><br/></td></tr>
<tr class="separator:a81be870dc9cfe995815d14bc106473a7"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:a2240f1d411f1eef6605ee6da1426c5ba"><td class="memItemLeft" align="right" valign="top">u32&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="xilskey__epl_8c.html#a2240f1d411f1eef6605ee6da1426c5ba">JtagAES_Check_Ultrascale</a> (u32 *Crc, u8 MarginOption)</td></tr>
<tr class="memdesc:a2240f1d411f1eef6605ee6da1426c5ba"><td class="mdescLeft">&#160;</td><td class="mdescRight">This function verifies the AES key of Ultrascale's EFUSE with provided CRC value.  <a href="#a2240f1d411f1eef6605ee6da1426c5ba">More...</a><br/></td></tr>
<tr class="separator:a2240f1d411f1eef6605ee6da1426c5ba"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:gab832f8fd82a6f4797eff212ff27fc3eb"><td class="memItemLeft" align="right" valign="top">u32&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__xilskey__zynq__ultra__efuse.html#gab832f8fd82a6f4797eff212ff27fc3eb">XilSKey_EfusePl_SystemInit</a> (<a class="el" href="struct_xil_s_key___e_pl.html">XilSKey_EPl</a> *InstancePtr)</td></tr>
<tr class="memdesc:gab832f8fd82a6f4797eff212ff27fc3eb"><td class="mdescLeft">&#160;</td><td class="mdescRight">Initializes PL eFUSE with input data given.  <a href="group__xilskey__zynq__ultra__efuse.html#gab832f8fd82a6f4797eff212ff27fc3eb">More...</a><br/></td></tr>
<tr class="separator:gab832f8fd82a6f4797eff212ff27fc3eb"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:gaf56f656aaae5bb0ebc9a3fee806fe202"><td class="memItemLeft" align="right" valign="top">u32&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__xilskey__zynq__ultra__efuse.html#gaf56f656aaae5bb0ebc9a3fee806fe202">XilSKey_EfusePl_Program</a> (<a class="el" href="struct_xil_s_key___e_pl.html">XilSKey_EPl</a> *InstancePtr)</td></tr>
<tr class="memdesc:gaf56f656aaae5bb0ebc9a3fee806fe202"><td class="mdescLeft">&#160;</td><td class="mdescRight">Programs PL eFUSE with input data given through InstancePtr.  <a href="group__xilskey__zynq__ultra__efuse.html#gaf56f656aaae5bb0ebc9a3fee806fe202">More...</a><br/></td></tr>
<tr class="separator:gaf56f656aaae5bb0ebc9a3fee806fe202"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga088a4e3919caebf725f3fdfaa1fecc41"><td class="memItemLeft" align="right" valign="top">u32&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__xilskey__zynq__ultra__efuse.html#ga088a4e3919caebf725f3fdfaa1fecc41">XilSKey_EfusePl_ReadStatus</a> (<a class="el" href="struct_xil_s_key___e_pl.html">XilSKey_EPl</a> *InstancePtr, u32 *StatusBits)</td></tr>
<tr class="memdesc:ga088a4e3919caebf725f3fdfaa1fecc41"><td class="mdescLeft">&#160;</td><td class="mdescRight">Reads the PL efuse status bits and gets all secure and control bits.  <a href="group__xilskey__zynq__ultra__efuse.html#ga088a4e3919caebf725f3fdfaa1fecc41">More...</a><br/></td></tr>
<tr class="separator:ga088a4e3919caebf725f3fdfaa1fecc41"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga9e00ec217ec5fce9cf298e92050c41db"><td class="memItemLeft" align="right" valign="top">u32&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__xilskey__zynq__ultra__efuse.html#ga9e00ec217ec5fce9cf298e92050c41db">XilSKey_EfusePl_ReadKey</a> (<a class="el" href="struct_xil_s_key___e_pl.html">XilSKey_EPl</a> *InstancePtr)</td></tr>
<tr class="memdesc:ga9e00ec217ec5fce9cf298e92050c41db"><td class="mdescLeft">&#160;</td><td class="mdescRight">Reads the PL efuse keys and stores them in the corresponding arrays in instance structure.  <a href="group__xilskey__zynq__ultra__efuse.html#ga9e00ec217ec5fce9cf298e92050c41db">More...</a><br/></td></tr>
<tr class="separator:ga9e00ec217ec5fce9cf298e92050c41db"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr><td colspan="2"><div class="groupHeader">API declarations</div></td></tr>
<tr><td colspan="2"><div class="groupText"><p>  </p>
</div></td></tr>
</table><table class="memberdecls">
<tr class="heading"><td colspan="2"><h2 class="groupheader"><a name="var-members"></a>
Variables</h2></td></tr>
<tr class="memitem:a23c3194fe5895df5dfc88b69dea9ee68"><td class="memItemLeft" align="right" valign="top">u32&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="xilskey__epl_8c.html#a23c3194fe5895df5dfc88b69dea9ee68">ErrorCode</a></td></tr>
<tr class="memdesc:a23c3194fe5895df5dfc88b69dea9ee68"><td class="mdescLeft">&#160;</td><td class="mdescRight">Global variable which holds the error key.  <a href="#a23c3194fe5895df5dfc88b69dea9ee68">More...</a><br/></td></tr>
<tr class="separator:a23c3194fe5895df5dfc88b69dea9ee68"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:a48a8908e1f7d0df90b4ea73dfcd8c99b"><td class="memItemLeft" align="right" valign="top">XSKEfusePl_Fpga&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="xilskey__epl_8c.html#a48a8908e1f7d0df90b4ea73dfcd8c99b">PlFpgaFlag</a></td></tr>
<tr class="memdesc:a48a8908e1f7d0df90b4ea73dfcd8c99b"><td class="mdescLeft">&#160;</td><td class="mdescRight">For Storing Fpga series.  <a href="#a48a8908e1f7d0df90b4ea73dfcd8c99b">More...</a><br/></td></tr>
<tr class="separator:a48a8908e1f7d0df90b4ea73dfcd8c99b"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ad332b969fb28da07cb32106cb4fbebf4"><td class="memItemLeft" align="right" valign="top">XilSKey_JtagSlr&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="xilskey__epl_8c.html#ad332b969fb28da07cb32106cb4fbebf4">XilSKeyJtag</a></td></tr>
<tr class="memdesc:ad332b969fb28da07cb32106cb4fbebf4"><td class="mdescLeft">&#160;</td><td class="mdescRight">JTAG Tap Instance.  <a href="#ad332b969fb28da07cb32106cb4fbebf4">More...</a><br/></td></tr>
<tr class="separator:ad332b969fb28da07cb32106cb4fbebf4"><td class="memSeparator" colspan="2">&#160;</td></tr>
</table>
<h2 class="groupheader">Macro Definition Documentation</h2>
<a class="anchor" id="abf99b08e9d05da21ca6433bc4373d776"></a>
<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define XSK_EFUSEPL_AES_ROW_END_ULTRA&#160;&#160;&#160;(27)</td>
        </tr>
      </table>
</div><div class="memdoc">

<p>AES key end row of FUSE for Ultrascale series. </p>

</div>
</div>
<a class="anchor" id="a4172b30afa58ba04a33d98520b492d5a"></a>
<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define XSK_EFUSEPL_AES_ROW_END_ULTRA_PLUS&#160;&#160;&#160;(20)</td>
        </tr>
      </table>
</div><div class="memdoc">

<p>AES key end row of FUSE for Ultrascale series. </p>

</div>
</div>
<a class="anchor" id="a6cbe0813ce06b0f5f109321ba9d9ba1d"></a>
<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define XSK_EFUSEPL_AES_ROW_START_ULTRA&#160;&#160;&#160;(20)</td>
        </tr>
      </table>
</div><div class="memdoc">

<p>AES key start row of FUSE for Ultrascale series. </p>

</div>
</div>
<a class="anchor" id="ad4da327de6c39915bf0bbe96673786b5"></a>
<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define XSK_EFUSEPL_AES_ROW_START_ULTRA_PLUS&#160;&#160;&#160;(5)</td>
        </tr>
      </table>
</div><div class="memdoc">

<p>AES key start row of FUSE for Ultrascale plus series. </p>

</div>
</div>
<a class="anchor" id="a12ddbe6f871054d07fba9f99cdd29a51"></a>
<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define XSK_EFUSEPL_ARRAY_AES_DATA_BITS_IN_30th_ROW&#160;&#160;&#160;(16)</td>
        </tr>
      </table>
</div><div class="memdoc">

<p>AES Data bits count in 30th Row. </p>

</div>
</div>
<a class="anchor" id="a022ba8260d6b2d7295617d1a1300a64b"></a>
<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define XSK_EFUSEPL_ARRAY_AES_DATA_ROW_END&#160;&#160;&#160;(30)</td>
        </tr>
      </table>
</div><div class="memdoc">

<p>AES Data End Row. </p>

</div>
</div>
<a class="anchor" id="ae448bfcfcaef65c918ea1dd9824ac8c7"></a>
<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define XSK_EFUSEPL_ARRAY_AES_DATA_ROW_START&#160;&#160;&#160;(20)</td>
        </tr>
      </table>
</div><div class="memdoc">

<p>AES Data Start Row. </p>

</div>
</div>
<a class="anchor" id="ac7c1f712a0206c5314fda54628c95ae5"></a>
<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define XSK_EFUSEPL_ARRAY_ECC_END_BIT_IN_A_ROW&#160;&#160;&#160;(29)</td>
        </tr>
      </table>
</div><div class="memdoc">

<p>ECC End Bit position in a Row. </p>

</div>
</div>
<a class="anchor" id="a0026a7af8fb8904232e5332c2464b7fb"></a>
<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define XSK_EFUSEPL_ARRAY_ECC_START_BIT_IN_A_ROW&#160;&#160;&#160;(24)</td>
        </tr>
      </table>
</div><div class="memdoc">

<p>ECC Start Bit position in a Row. </p>

</div>
</div>
<a class="anchor" id="af56a0efea5eed4f50203a71462eb7bf8"></a>
<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define XSK_EFUSEPL_ARRAY_FUSE_128BIT_USER_SIZE&#160;&#160;&#160;(128)</td>
        </tr>
      </table>
</div><div class="memdoc">

<p>128 bit User key size </p>

</div>
</div>
<a class="anchor" id="a6c30e3653be249cb96ae7b04007993ff"></a>
<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define XSK_EFUSEPL_ARRAY_FUSE_AES_KEY_SIZE&#160;&#160;&#160;(256)</td>
        </tr>
      </table>
</div><div class="memdoc">

<p>AES Key size. </p>

</div>
</div>
<a class="anchor" id="ae3f3d33727652dc2eb86175ef47d0215"></a>
<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define XSK_EFUSEPL_ARRAY_FUSE_CNTRL_END_BIT&#160;&#160;&#160;(10)</td>
        </tr>
      </table>
</div><div class="memdoc">

<p>Fuse Control Start bit. </p>

</div>
</div>
<a class="anchor" id="a781f58a79e9dd399569744ac5b692213"></a>
<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define XSK_EFUSEPL_ARRAY_FUSE_CNTRL_MAX_BITS&#160;&#160;&#160;(11)</td>
        </tr>
      </table>
</div><div class="memdoc">

<p>Fuse Control max bits. </p>

</div>
</div>
<a class="anchor" id="a655b038e7764d378fdb39efc9b6e344c"></a>
<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define XSK_EFUSEPL_ARRAY_FUSE_CNTRL_REDUNDENT_END_BIT&#160;&#160;&#160;(24)</td>
        </tr>
      </table>
</div><div class="memdoc">

<p>Redundant bit End Index. </p>

</div>
</div>
<a class="anchor" id="a644213b51656a2f94957634aafe0ed62"></a>
<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define XSK_EFUSEPL_ARRAY_FUSE_CNTRL_REDUNDENT_INDEX&#160;&#160;&#160;(14)</td>
        </tr>
      </table>
</div><div class="memdoc">

<p>Redundant bit Index. </p>

</div>
</div>
<a class="anchor" id="acc49ad5b76e54ed8c1817b21c3438b98"></a>
<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define XSK_EFUSEPL_ARRAY_FUSE_CNTRL_REDUNDENT_START_BIT&#160;&#160;&#160;(14)</td>
        </tr>
      </table>
</div><div class="memdoc">

<p>Redundant bit start Index. </p>

</div>
</div>
<a class="anchor" id="ad9ff84e6d99e4e3bac14409dd6912c69"></a>
<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define XSK_EFUSEPL_ARRAY_FUSE_CNTRL_ROW&#160;&#160;&#160;(0)</td>
        </tr>
      </table>
</div><div class="memdoc">

<p>Fuse Ctrl Row. </p>

</div>
</div>
<a class="anchor" id="a73335e64a5e63bed5ee3c787ae41231e"></a>
<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define XSK_EFUSEPL_ARRAY_FUSE_CNTRL_START_BIT&#160;&#160;&#160;(0)</td>
        </tr>
      </table>
</div><div class="memdoc">

<p>Fuse Control Start bit. </p>

</div>
</div>
<a class="anchor" id="a7edd630a1c41c7c2f84afbce254374bb"></a>
<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define XSK_EFUSEPL_ARRAY_FUSE_USER_KEY_SIZE&#160;&#160;&#160;(32)</td>
        </tr>
      </table>
</div><div class="memdoc">

<p>32 bit User key size </p>

</div>
</div>
<a class="anchor" id="a668c1b4f2d82a98eaf65a1db86e4e02a"></a>
<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define XSK_EFUSEPL_ARRAY_MAX_COL&#160;&#160;&#160;(32)</td>
        </tr>
      </table>
</div><div class="memdoc">

<p>PLeFUSE Max Columns. </p>

</div>
</div>
<a class="anchor" id="a3b7696823424128e5ef4cd6c8ca33c8d"></a>
<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define XSK_EFUSEPL_ARRAY_MAX_COL_ULTRA_PLUS&#160;&#160;&#160;(16)</td>
        </tr>
      </table>
</div><div class="memdoc">

<p>Ultrascale plus max bits in a row. </p>

</div>
</div>
<a class="anchor" id="a1d2d8ec9ed54ca749fc668c28b7dc3f3"></a>
<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define XSK_EFUSEPL_ARRAY_MAX_ECC_BITS_IN_A_ROW&#160;&#160;&#160;(6)</td>
        </tr>
      </table>
</div><div class="memdoc">

<p>Max ECC bits in a Row. </p>

</div>
</div>
<a class="anchor" id="a9a9a93463a883b1d6149d8f7b24c7027"></a>
<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define XSK_EFUSEPL_ARRAY_MAX_PAYLAOD_BITS_IN_A_ROW&#160;&#160;&#160;(24)</td>
        </tr>
      </table>
</div><div class="memdoc">

<p>Max Pay load in Row. </p>

</div>
</div>
<a class="anchor" id="ac54e5d005493b56b5ff983749aaf77d6"></a>
<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define XSK_EFUSEPL_ARRAY_MAX_ROW&#160;&#160;&#160;(32)</td>
        </tr>
      </table>
</div><div class="memdoc">

<p>PLeFUSE Max Rows. </p>

</div>
</div>
<a class="anchor" id="a37bb569c0fc819a6a36e6a43c389b165"></a>
<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define XSK_EFUSEPL_ARRAY_UNSUPPORTED_BIT6&#160;&#160;&#160;(6)</td>
        </tr>
      </table>
</div><div class="memdoc">

<p>Unsupported bit. </p>

</div>
</div>
<a class="anchor" id="ae3da6e05934b601952121d2d32f80ec5"></a>
<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define XSK_EFUSEPL_ARRAY_UNSUPPORTED_BIT7&#160;&#160;&#160;(7)</td>
        </tr>
      </table>
</div><div class="memdoc">

<p>Unsupporte bit. </p>

</div>
</div>
<a class="anchor" id="a35bc722e37bbf9b89c3f92def4823bb8"></a>
<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define XSK_EFUSEPL_ARRAY_UNSUPPORTED_RED_FOR_BIT6&#160;&#160;&#160;(20)</td>
        </tr>
      </table>
</div><div class="memdoc">

<p>Unsupported bit. </p>

</div>
</div>
<a class="anchor" id="a52da5afc1f49a09f9f2a7faac4fa1746"></a>
<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define XSK_EFUSEPL_ARRAY_UNSUPPORTED_RED_FOR_BIT7&#160;&#160;&#160;(21)</td>
        </tr>
      </table>
</div><div class="memdoc">

<p>Unsupported bit. </p>

</div>
</div>
<a class="anchor" id="a8ba85117e55c4c6da5560f44ee4cd2e0"></a>
<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define XSK_EFUSEPL_ARRAY_USER_DATA_BITS_IN_30th_ROW&#160;&#160;&#160;(8)</td>
        </tr>
      </table>
</div><div class="memdoc">

<p>User Data bits count in 30th Row. </p>

</div>
</div>
<a class="anchor" id="a8aab974df3392caeb65986fa2322247d"></a>
<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define XSK_EFUSEPL_ARRAY_USER_DATA_START_ROW&#160;&#160;&#160;(31)</td>
        </tr>
      </table>
</div><div class="memdoc">

<p>User Data Start Row. </p>

</div>
</div>
<a class="anchor" id="a6117759030cf75eaefaaf08523343290"></a>
<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define XSK_EFUSEPL_CNTRL_MAX_BITS_ULTRA&#160;&#160;&#160;(17)</td>
        </tr>
      </table>
</div><div class="memdoc">

<p>Fuse Control max bits of Ultrascale series. </p>

</div>
</div>
<a class="anchor" id="a080554ab1580195d3bacbb36651a5906"></a>
<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define XSK_EFUSEPL_CNTRL_ROW_END_ULTRA_PLUS&#160;&#160;&#160;(3)</td>
        </tr>
      </table>
</div><div class="memdoc">

<p>Control row of FUSE for Ultrascale plus series. </p>

</div>
</div>
<a class="anchor" id="a7d46ae55e8a8445adb7d03fcd271f34d"></a>
<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define XSK_EFUSEPL_CNTRL_ROW_START_ULTRA_PLUS&#160;&#160;&#160;(2)</td>
        </tr>
      </table>
</div><div class="memdoc">

<p>Control row of FUSE for Ultrascale plus series. </p>

</div>
</div>
<a class="anchor" id="ab57e87661cd1c70cdfc11764aa741ef1"></a>
<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define XSK_EFUSEPL_CNTRL_ROW_ULTRA&#160;&#160;&#160;(1)</td>
        </tr>
      </table>
</div><div class="memdoc">

<p>Control row of FUSE for Ultrascale series. </p>

</div>
</div>
<a class="anchor" id="a7a3dfa1dc75df17382769bc43392dc3e"></a>
<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define XSK_EFUSEPL_CTRL_ROW_END_BIT_ULTRA&#160;&#160;&#160;(16)</td>
        </tr>
      </table>
</div><div class="memdoc">

<p>Control row end bit of Ultrascale series. </p>

</div>
</div>
<a class="anchor" id="a45aabab52e0458600e145ccbfa1404a2"></a>
<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define XSK_EFUSEPL_CTRL_ROW_UNSUPPORT_BIT3_ULTRA&#160;&#160;&#160;(3)</td>
        </tr>
      </table>
</div><div class="memdoc">

<p>Unsupported bits of Control register. </p>

</div>
</div>
<a class="anchor" id="a0addc2b729efcd07c5e8321ce42bf079"></a>
<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define XSK_EFUSEPL_CTRL_ROW_UNSUPPORT_BIT4_ULTRA&#160;&#160;&#160;(4)</td>
        </tr>
      </table>
</div><div class="memdoc">

<p>&lt; Unsupported bit in ctrl register </p>

</div>
</div>
<a class="anchor" id="ae27dbc5b15b3c278543e67efddf6f898"></a>
<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define XSK_EFUSEPL_CTRL_ROW_UNSUPPORT_BIT_RANGE_END_ULTRA&#160;&#160;&#160;(14)</td>
        </tr>
      </table>
</div><div class="memdoc">

<p>&lt; Unsupported bit in ctrl register </p>

</div>
</div>
<a class="anchor" id="a5b7d16d963896034d14f97703d25c9f6"></a>
<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define XSK_EFUSEPL_CTRL_ROW_UNSUPPORT_BIT_RANGE_START_ULTRA&#160;&#160;&#160;(10)</td>
        </tr>
      </table>
</div><div class="memdoc">

<p>&lt; Unsupported bit in ctrl register </p>

</div>
</div>
<a class="anchor" id="a54f3f565380021d2942a1e690420cd78"></a>
<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define XSK_EFUSEPL_DNA_KEY_SIZE_ULTRA&#160;&#160;&#160;(96)</td>
        </tr>
      </table>
</div><div class="memdoc">

<p>DNA key size of Ultrascale series. </p>

</div>
</div>
<a class="anchor" id="a983af8e67d61c9741c53beeecac61faa"></a>
<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define XSK_EFUSEPL_DNA_ROW_END_ULTRA_PLUS&#160;&#160;&#160;(5)</td>
        </tr>
      </table>
</div><div class="memdoc">

<p>DNA row of FUSE for Ultrascale plus series. </p>

</div>
</div>
<a class="anchor" id="aa87ad616f07a06341e160e33727c695b"></a>
<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define XSK_EFUSEPL_DNA_ROW_START_ULTRA_PLUS&#160;&#160;&#160;(0)</td>
        </tr>
      </table>
</div><div class="memdoc">

<p>DNA row of FUSE for Ultrascale plus series. </p>

</div>
</div>
<a class="anchor" id="a1db1953a12bf1e0690df83306e18cfbc"></a>
<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define XSK_EFUSEPL_DNA_ROW_ULTRA&#160;&#160;&#160;(7)</td>
        </tr>
      </table>
</div><div class="memdoc">

<p>DNA row of FUSE for Ultrascale series. </p>

</div>
</div>
<a class="anchor" id="ab744c4486807f8f5fc9ff5d85152ff6a"></a>
<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define XSK_EFUSEPL_END_BIT_IN_A_ROW_ULTRA&#160;&#160;&#160;(31)</td>
        </tr>
      </table>
</div><div class="memdoc">

<p>FUSE end bit in a row of Ultrascale series. </p>

</div>
</div>
<a class="anchor" id="a36c79b15c321dade60032001215f949d"></a>
<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define XSK_EFUSEPL_MAX_BITS_IN_A_ROW_ULTRA&#160;&#160;&#160;(32)</td>
        </tr>
      </table>
</div><div class="memdoc">

<p>Max Pay load in Row. </p>

</div>
</div>
<a class="anchor" id="a8dab4092fffc9c9ef6d80843f98ef457"></a>
<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define XSK_EFUSEPL_MAX_REF_CLK_FREQ&#160;&#160;&#160;60000000</td>
        </tr>
      </table>
</div><div class="memdoc">

<p>Max Ref Clk Frequency. </p>
<p>&lt; Unsupported bit in ctrl register</p>
<p>Max Ref Clk Frequency </p>

</div>
</div>
<a class="anchor" id="a8dab4092fffc9c9ef6d80843f98ef457"></a>
<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define XSK_EFUSEPL_MAX_REF_CLK_FREQ&#160;&#160;&#160;60000000</td>
        </tr>
      </table>
</div><div class="memdoc">

<p>Max Ref Clk Frequency. </p>
<p>&lt; Unsupported bit in ctrl register</p>
<p>Max Ref Clk Frequency </p>

</div>
</div>
<a class="anchor" id="ab595634f414538c8c30052c2719f3bf4"></a>
<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define XSK_EFUSEPL_MIN_REF_CLK_FREQ&#160;&#160;&#160;20000000</td>
        </tr>
      </table>
</div><div class="memdoc">

<p>Min Ref Clk Frequency. </p>

</div>
</div>
<a class="anchor" id="ab595634f414538c8c30052c2719f3bf4"></a>
<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define XSK_EFUSEPL_MIN_REF_CLK_FREQ&#160;&#160;&#160;20000000</td>
        </tr>
      </table>
</div><div class="memdoc">

<p>Min Ref Clk Frequency. </p>

</div>
</div>
<a class="anchor" id="a5c55c664fa9ebd10dffae1f6af853239"></a>
<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define XSK_EFUSEPL_NORMAL_ULTRA&#160;&#160;&#160;(0)</td>
        </tr>
      </table>
</div><div class="memdoc">

<p>Normal read selection for Ultrascale series. </p>

</div>
</div>
<a class="anchor" id="a8d3288d93ff8fbb642c62fda2318014f"></a>
<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define XSK_EFUSEPL_PAGE_0_ULTRA&#160;&#160;&#160;(0)</td>
        </tr>
      </table>
</div><div class="memdoc">

<p>Page 0 for Ultrascale series. </p>

</div>
</div>
<a class="anchor" id="a33e4b4e324f30f256e29d644bf16f840"></a>
<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define XSK_EFUSEPL_PAGE_1_ULTRA&#160;&#160;&#160;(1)</td>
        </tr>
      </table>
</div><div class="memdoc">

<p>Page 1 for Ultrascale series. </p>

</div>
</div>
<a class="anchor" id="a12be050ae2a88b04c6a5401dd9c1f4b7"></a>
<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define XSK_EFUSEPL_REDUNDANT_ULTRA&#160;&#160;&#160;(1)</td>
        </tr>
      </table>
</div><div class="memdoc">

<p>Redundant read selection for Ultrascale series. </p>

</div>
</div>
<a class="anchor" id="a73b84216f2b538ec2e08411108d2b555"></a>
<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define XSK_EFUSEPL_RSA_HASH_SIZE_ULTRA&#160;&#160;&#160;(384)</td>
        </tr>
      </table>
</div><div class="memdoc">

<p>RSA hash size of Ultrascale series. </p>

</div>
</div>
<a class="anchor" id="a9701f48edeb1d8f13ad2afe1b7884a4a"></a>
<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define XSK_EFUSEPL_RSA_ROW_END_ULTRA&#160;&#160;&#160;(23)</td>
        </tr>
      </table>
</div><div class="memdoc">

<p>RSA end row of FUSE for Ultrascale series. </p>

</div>
</div>
<a class="anchor" id="aa69b916adceb1705aaa056e34cb3b853"></a>
<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define XSK_EFUSEPL_RSA_ROW_END_ULTRA_PLUS&#160;&#160;&#160;(29)</td>
        </tr>
      </table>
</div><div class="memdoc">

<p>RSA end row of FUSE for Ultrascale plus series. </p>

</div>
</div>
<a class="anchor" id="a5cb41e0920367bf4203baaad5d3ac831"></a>
<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define XSK_EFUSEPL_RSA_ROW_START_ULTRA&#160;&#160;&#160;(12)</td>
        </tr>
      </table>
</div><div class="memdoc">

<p>RSA start row of FUSE for Ultrascale series. </p>

</div>
</div>
<a class="anchor" id="a10fa4c8974224924541dbd93f1116c0f"></a>
<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define XSK_EFUSEPL_RSA_ROW_START_ULTRA_PLUS&#160;&#160;&#160;(6)</td>
        </tr>
      </table>
</div><div class="memdoc">

<p>RSA start row of FUSE for Ultrascale plus series. </p>

</div>
</div>
<a class="anchor" id="a24936d81214b465d69ad46ed94c663ec"></a>
<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define XSK_EFUSEPL_SEC_MAX_BITS_ULTRA&#160;&#160;&#160;(7)</td>
        </tr>
      </table>
</div><div class="memdoc">

<p>Secure row max bits of Ultrascale series. </p>

</div>
</div>
<a class="anchor" id="a5575a15d9850c63df2e6b611916ef242"></a>
<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define XSK_EFUSEPL_SEC_ROW_END_BIT_ULTRA&#160;&#160;&#160;(6)</td>
        </tr>
      </table>
</div><div class="memdoc">

<p>Secure row end bit of Ultrascale series. </p>

</div>
</div>
<a class="anchor" id="aa0eea2bede212c5830e83cba4cd6ed68"></a>
<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define XSK_EFUSEPL_SEC_ROW_ULTRA&#160;&#160;&#160;(10)</td>
        </tr>
      </table>
</div><div class="memdoc">

<p>Secure row of FUSE for Ultrascale series. </p>

</div>
</div>
<a class="anchor" id="a4028e62af94e327b59fe19e88d50954a"></a>
<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define XSK_EFUSEPL_SEC_ROW_ULTRA_PLUS&#160;&#160;&#160;(4)</td>
        </tr>
      </table>
</div><div class="memdoc">

<p>Secure row of FUSE for Ultrascale series. </p>

</div>
</div>
<a class="anchor" id="a301acab7bc3bd402dde525139913ea58"></a>
<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define XSK_EFUSEPL_USER_128BIT_ROW_END_ULTRA&#160;&#160;&#160;(3)</td>
        </tr>
      </table>
</div><div class="memdoc">

<p>128 bit USER key end row of FUSE for Ultrascale series </p>

</div>
</div>
<a class="anchor" id="a720c60fbb27fbc6a4da2250b46cadd42"></a>
<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define XSK_EFUSEPL_USER_128BIT_ROW_END_ULTRA_PLUS&#160;&#160;&#160;(28)</td>
        </tr>
      </table>
</div><div class="memdoc">

<p>128 bit USER key end row of FUSE for Ultrascale plus series </p>

</div>
</div>
<a class="anchor" id="a45b5de44e94a45932de0f0d958fc668a"></a>
<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define XSK_EFUSEPL_USER_128BIT_ROW_START_ULTRA&#160;&#160;&#160;(0)</td>
        </tr>
      </table>
</div><div class="memdoc">

<p>128 bit USER key start row of FUSE for Ultrascale series </p>

</div>
</div>
<a class="anchor" id="a08c0decf4b0fff61451eb2b694e1af29"></a>
<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define XSK_EFUSEPL_USER_128BIT_ROW_START_ULTRA_PLUS&#160;&#160;&#160;(21)</td>
        </tr>
      </table>
</div><div class="memdoc">

<p>128 bit USER key start row of FUSE for Ultrascale plus series </p>

</div>
</div>
<a class="anchor" id="a8a7c1770654fbe08d533f6b9496d015a"></a>
<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define XSK_EFUSEPL_USER_ROW_END_ULTRA_PLUS&#160;&#160;&#160;(31)</td>
        </tr>
      </table>
</div><div class="memdoc">

<p>USER key start row of FUSE for Ultrascale plus series. </p>

</div>
</div>
<a class="anchor" id="afcaada162bdd5661a7338a059de68af0"></a>
<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define XSK_EFUSEPL_USER_ROW_START_ULTRA_PLUS&#160;&#160;&#160;(30)</td>
        </tr>
      </table>
</div><div class="memdoc">

<p>USER key start row of FUSE for Ultrascale plus series. </p>

</div>
</div>
<a class="anchor" id="ab81b69f44f409d9b8ea3cae46991a784"></a>
<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define XSK_EFUSEPL_USER_ROW_ULTRA&#160;&#160;&#160;(28)</td>
        </tr>
      </table>
</div><div class="memdoc">

<p>USER key start row of FUSE for Ultrascale series. </p>

</div>
</div>
<h2 class="groupheader">Enumeration Type Documentation</h2>
<a class="anchor" id="a4f87dd891cf4f17bd68a9820622917d5"></a>
<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">enum <a class="el" href="xilskey__epl_8c.html#a4f87dd891cf4f17bd68a9820622917d5">XSK_EfusePl_MarginOption</a></td>
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<p>Read or Write eFUSE Margin Options. </p>
<table class="fieldtable">
<tr><th colspan="2">Enumerator</th></tr><tr><td class="fieldname"><em><a class="anchor" id="a4f87dd891cf4f17bd68a9820622917d5aff7202698f203b2ec237193f55537b0c"></a>XSK_EFUSEPL_READ_NORMAL</em>&nbsp;</td><td class="fielddoc">
<p>Margin 1. </p>
</td></tr>
<tr><td class="fieldname"><em><a class="anchor" id="a4f87dd891cf4f17bd68a9820622917d5a6d4355c10eef92db810e21fb8a987c91"></a>XSK_EFUSEPL_READ_MARGIN_1</em>&nbsp;</td><td class="fielddoc">
<p>Margin 2. </p>
</td></tr>
<tr><td class="fieldname"><em><a class="anchor" id="a4f87dd891cf4f17bd68a9820622917d5a264bbce97fef27d2300c0bb4e4080329"></a>XSK_EFUSEPL_READ_MARGIN_2</em>&nbsp;</td><td class="fielddoc">
<p>Margin 4. </p>
</td></tr>
<tr><td class="fieldname"><em><a class="anchor" id="a4f87dd891cf4f17bd68a9820622917d5aef053ed40f210a230d2efd471ef3a5df"></a>XSK_EFUSEPL_READ_MARGIN_MAX</em>&nbsp;</td><td class="fielddoc">
<p>Max Margin 7. </p>
</td></tr>
</table>

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          <td class="memname">enum <a class="el" href="xilskey__epl_8c.html#ad788ed0003b0c5dcb8b56ad9c34961de">XSKEfusePl_FuseCntrlBits</a></td>
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<p>Fuse Control Row Bit Indices. </p>
<table class="fieldtable">
<tr><th colspan="2">Enumerator</th></tr><tr><td class="fieldname"><em><a class="anchor" id="ad788ed0003b0c5dcb8b56ad9c34961dea564ab9c065e6fe01852339b6a334d1ab"></a>XSK_EFUSEPL_CNTRL_FORCE_PCYCLE_RECONFIG</em>&nbsp;</td><td class="fielddoc">
<p>Bit1 of Fuse Ctrl Row. </p>
</td></tr>
<tr><td class="fieldname"><em><a class="anchor" id="ad788ed0003b0c5dcb8b56ad9c34961dea2d2072c692c5f90cdde64e7297f0cb5c"></a>XSK_EFUSEPL_CNTRL_DISABLE_KEY_WRITE</em>&nbsp;</td><td class="fielddoc">
<p>Bit2 of Fuse Ctrl Row. </p>
</td></tr>
<tr><td class="fieldname"><em><a class="anchor" id="ad788ed0003b0c5dcb8b56ad9c34961dea9654c58aff7a6ddc2c4cf85ba520cfe5"></a>XSK_EFUSEPL_CNTRL_DISABLE_AES_KEY_READ</em>&nbsp;</td><td class="fielddoc">
<p>Bit3 of Fuse Ctrl Row. </p>
</td></tr>
<tr><td class="fieldname"><em><a class="anchor" id="ad788ed0003b0c5dcb8b56ad9c34961deacc5ba1a4a66dffce7060cabece3036a7"></a>XSK_EFUSEPL_CNTRL_DISABLE_USER_KEY_READ</em>&nbsp;</td><td class="fielddoc">
<p>Bit4 of Fuse Ctrl Row. </p>
</td></tr>
<tr><td class="fieldname"><em><a class="anchor" id="ad788ed0003b0c5dcb8b56ad9c34961deab750d0e7bad9ce3b945cae613e1a8148"></a>XSK_EFUSEPL_CNTRL_DISABLE_FUSE_CNTRL_WRITE</em>&nbsp;</td><td class="fielddoc">
<p>Bit5 of Fuse Ctrl Row. </p>
</td></tr>
<tr><td class="fieldname"><em><a class="anchor" id="ad788ed0003b0c5dcb8b56ad9c34961dea25c43fe81e29a37602dc86038feb0d12"></a>XSK_EFUSEPL_CNTRL_FORCE_USE_AES_ONLY</em>&nbsp;</td><td class="fielddoc">
<p>Bit8 of Fuse Ctrl Row. </p>
</td></tr>
<tr><td class="fieldname"><em><a class="anchor" id="ad788ed0003b0c5dcb8b56ad9c34961dea0b45e58b49a9ce025978d2fa3f0584d0"></a>XSK_EFUSEPL_CNTRL_JTAG_CHAIN_DISABLE</em>&nbsp;</td><td class="fielddoc">
<p>Bit9 of Fuse Ctrl Row. </p>
</td></tr>
<tr><td class="fieldname"><em><a class="anchor" id="ad788ed0003b0c5dcb8b56ad9c34961deaf165e629ce040fd70086730f877890a9"></a>XSK_EFUSEPL_CNTRL_BBRAM_KEY_DISABLE</em>&nbsp;</td><td class="fielddoc">
<p>Bit10 of Fuse Ctrl Row. </p>
</td></tr>
</table>

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<p>Fuse Control Row Bit Indices of Ultrascale series. </p>
<table class="fieldtable">
<tr><th colspan="2">Enumerator</th></tr><tr><td class="fieldname"><em><a class="anchor" id="ac9a38d78264d1de965de9ea375b7486fa9f12db83dcd56d735b3d3db595eb5bbb"></a>XSK_EFUSEPL_CNTRL_DISABLE_KEY_RD_ULTRA</em>&nbsp;</td><td class="fielddoc">
<p>Bit 0 of Fuse Ctrl row of Ultrascale. </p>
</td></tr>
<tr><td class="fieldname"><em><a class="anchor" id="ac9a38d78264d1de965de9ea375b7486faccd7ea296b35f2b1edeb6cdd32645d8f"></a>XSK_EFUSEPL_CNTRL_DISABLE_USER_KEY_RD_ULTRA</em>&nbsp;</td><td class="fielddoc">
<p>Bit 1 of Fuse Ctrl row of Ultrascale. </p>
</td></tr>
<tr><td class="fieldname"><em><a class="anchor" id="ac9a38d78264d1de965de9ea375b7486faf8ade165a1c788079deb288b3bcf906a"></a>XSK_EFUSEPL_CNTRL_DISABLE_SEC_RD_ULTRA</em>&nbsp;</td><td class="fielddoc">
<p>Bit 2 of Fuse Ctrl row of Ultrascale. </p>
</td></tr>
<tr><td class="fieldname"><em><a class="anchor" id="ac9a38d78264d1de965de9ea375b7486fa2c25d3a65e34751ebd2ec70c6949f7c1"></a>XSK_EFUSEPL_CNTRL_DISABLE_CNTRL_WR_ULTRA</em>&nbsp;</td><td class="fielddoc">
<p>Bit 5 of Fuse Ctrl row of Ultrascale. </p>
</td></tr>
<tr><td class="fieldname"><em><a class="anchor" id="ac9a38d78264d1de965de9ea375b7486faf17bb1f794362faa4a0d1e6e67d2dceb"></a>XSK_EFUSEPL_CNTRL_DISABLE_RSA_KEY_RD_ULTRA</em>&nbsp;</td><td class="fielddoc">
<p>Bit 6 of Fuse Ctrl row of Ultrascale. </p>
</td></tr>
<tr><td class="fieldname"><em><a class="anchor" id="ac9a38d78264d1de965de9ea375b7486faca83d34b380088bbc30592632bf7a935"></a>XSK_EFUSEPL_CNTRL_DISABLE_KEY_WR_ULTRA</em>&nbsp;</td><td class="fielddoc">
<p>Bit 7 of Fuse Ctrl row of Ultrascale. </p>
</td></tr>
<tr><td class="fieldname"><em><a class="anchor" id="ac9a38d78264d1de965de9ea375b7486fa681b7a86d2cb18443929764e200608bd"></a>XSK_EFUSEPL_CNTRL_DISABLE_USER_KEY_WR_ULTRA</em>&nbsp;</td><td class="fielddoc">
<p>Bit 8 of Fuse Ctrl row of Ultrascale. </p>
</td></tr>
<tr><td class="fieldname"><em><a class="anchor" id="ac9a38d78264d1de965de9ea375b7486fa2c60152852ba70d49741c4364e542596"></a>XSK_EFUSEPL_CNTRL_DISABLE_SEC_WR_ULTRA</em>&nbsp;</td><td class="fielddoc">
<p>Bit 8 of Fuse Ctrl row of Ultrascale. </p>
</td></tr>
<tr><td class="fieldname"><em><a class="anchor" id="ac9a38d78264d1de965de9ea375b7486fa8bde903764407a85423d4f01082d4961"></a>XSK_EFUSEPL_CNTRL_DISABLE_RSA_KEY_WR_ULTRA</em>&nbsp;</td><td class="fielddoc">
<p>Bit 15 of Fuse Ctrl row of Ultrascale. </p>
</td></tr>
<tr><td class="fieldname"><em><a class="anchor" id="ac9a38d78264d1de965de9ea375b7486fa5f3b141d98f753bae39ea1924ae35bc5"></a>XSK_EFUSEPL_CNTRL_DISABLE_128BIT_USR_KEY_WR_ULTRA</em>&nbsp;</td><td class="fielddoc">
<p>Bit 16 of Fuse Ctrl row of Ultrascale. </p>
</td></tr>
</table>

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          <td class="memname">enum <a class="el" href="xilskey__epl_8c.html#ac9b6d5e426c9bbc6af1138801bf8e1ca">XSKEfusePl_FuseSecureBits_Ultra</a></td>
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<p>Fuse Secure Row Bit Indices of Ultrascale series. </p>
<table class="fieldtable">
<tr><th colspan="2">Enumerator</th></tr><tr><td class="fieldname"><em><a class="anchor" id="ac9b6d5e426c9bbc6af1138801bf8e1caa1f950d11fb2fd1f1acbf7fe7a0a02176"></a>XSK_EFUSEPL_SEC_ALLOW_ENCRYPT_ONLY</em>&nbsp;</td><td class="fielddoc">
<p>Bit 0 of Fuse Secure row of Ultrascale. </p>
</td></tr>
<tr><td class="fieldname"><em><a class="anchor" id="ac9b6d5e426c9bbc6af1138801bf8e1caa2cddeeb70f3e8f6b0f94b46f138ccd6e"></a>XSK_EFUSEPL_SEC_FORCE_AES_ONLY_ULTRA</em>&nbsp;</td><td class="fielddoc">
<p>Bit 1 of Fuse Secure row of Ultrascale. </p>
</td></tr>
<tr><td class="fieldname"><em><a class="anchor" id="ac9b6d5e426c9bbc6af1138801bf8e1caad65d494b7924ac982cb826c4213fa858"></a>XSK_EFUSEPL_SEC_RSA_AUTH_EN_ULTRA</em>&nbsp;</td><td class="fielddoc">
<p>Bit 2 of Fuse Secure row of Ultrascale. </p>
</td></tr>
<tr><td class="fieldname"><em><a class="anchor" id="ac9b6d5e426c9bbc6af1138801bf8e1caa14662984cc3828fcb3ba223d4f104a97"></a>XSK_EFUSEPL_SEC_JTAG_CHAIN_DISABLE_ULTRA</em>&nbsp;</td><td class="fielddoc">
<p>Bit 3 of Fuse Secure row of Ultrascale. </p>
</td></tr>
<tr><td class="fieldname"><em><a class="anchor" id="ac9b6d5e426c9bbc6af1138801bf8e1caacc2d06b97690397fc05fc49992045666"></a>XSK_EFUSEPL_SEC_DISABLE_INTRNL_TEST_ACCESS_ULTRA</em>&nbsp;</td><td class="fielddoc">
<p>Bit 4 of Fuse Secure row of Ultrascale. </p>
</td></tr>
<tr><td class="fieldname"><em><a class="anchor" id="ac9b6d5e426c9bbc6af1138801bf8e1caad875450d5ae299147ca224c51326c2ae"></a>XSK_EFUSEPL_SEC_DISABLE_DECRPTR_ULTRA</em>&nbsp;</td><td class="fielddoc">
<p>Bit 5 of Fuse Secure row of Ultrascale. </p>
</td></tr>
<tr><td class="fieldname"><em><a class="anchor" id="ac9b6d5e426c9bbc6af1138801bf8e1caad23d8f5886a446c350c4c821e008c09c"></a>XSK_EFUSEPL_SEC_ENABLE_OBFUSCATION_ULTRA</em>&nbsp;</td><td class="fielddoc">
<p>Bit 6 of fuse secure row row of Ultrascale. </p>
</td></tr>
</table>

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<h2 class="groupheader">Function Documentation</h2>
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          <td class="memname">u32 JtagAES_Check_Ultrascale </td>
          <td>(</td>
          <td class="paramtype">u32 *&#160;</td>
          <td class="paramname"><em>Crc</em>, </td>
        </tr>
        <tr>
          <td class="paramkey"></td>
          <td></td>
          <td class="paramtype">u8&#160;</td>
          <td class="paramname"><em>MarginOption</em>&#160;</td>
        </tr>
        <tr>
          <td></td>
          <td>)</td>
          <td></td><td></td>
        </tr>
      </table>
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<p>This function verifies the AES key of Ultrascale's EFUSE with provided CRC value. </p>
<dl class="params"><dt>Parameters</dt><dd>
  <table class="params">
    <tr><td class="paramname">Crc</td><td>is a pointer to a 32 bit variable which holds the expected AES key's CRC. </td></tr>
    <tr><td class="paramname">MarginOption</td><td>is a variable which tells the margin option in which read operation to be performed.</td></tr>
  </table>
  </dd>
</dl>
<dl class="section return"><dt>Returns</dt><dd>Returns XST_FAILURE/XST_SUCCESS<ul>
<li>XST_SUCCESS - If CRC is correct</li>
<li>XST_FAILURE - If CRC is wrong</li>
</ul>
</dd></dl>
<dl class="section note"><dt>Note</dt><dd>To verify AES key with provided CRC 256 bits need to be written with all ZEROS and last 32 bits with CRC. And then CTS word should be framed and read 9 rows. The keys are stored in 8 rows (20 to 27) but in UltraScale the device will read all 1s. On the 9th read (row 28), the CRC computation takes place. An extra read after the 9th read is required to read the computed CRC out (can use last row addr of 28 or row 0). The FPGA internally compares the computed CRC with the expected CRC loaded through the FUSE_KEY operation. If they match, then the expected CRC is read. If not, the FPGA will return all 1s. </dd></dl>

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          <td class="memname">void JtagRead </td>
          <td>(</td>
          <td class="paramtype">unsigned char&#160;</td>
          <td class="paramname"><em>row</em>, </td>
        </tr>
        <tr>
          <td class="paramkey"></td>
          <td></td>
          <td class="paramtype">unsigned int *&#160;</td>
          <td class="paramname"><em>row_data</em>, </td>
        </tr>
        <tr>
          <td class="paramkey"></td>
          <td></td>
          <td class="paramtype">unsigned char&#160;</td>
          <td class="paramname"><em>marginOption</em>&#160;</td>
        </tr>
        <tr>
          <td></td>
          <td>)</td>
          <td></td><td></td>
        </tr>
      </table>
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<p>JTAG Server Read routine. </p>

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          <td class="memname">void JtagRead_Status_Ultrascale </td>
          <td>(</td>
          <td class="paramtype">u32 *&#160;</td>
          <td class="paramname"><em>Rowdata</em></td><td>)</td>
          <td></td>
        </tr>
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<p>This function reads the status row of Ultrascale's EFUSE and updates the pointer. </p>
<dl class="params"><dt>Parameters</dt><dd>
  <table class="params">
    <tr><td class="paramname">Rowdata</td><td>is a pointer to a 32 bit variable which stores the status register value read from EFUSE status register.</td></tr>
  </table>
  </dd>
</dl>
<dl class="section return"><dt>Returns</dt><dd>None.</dd></dl>
<dl class="section note"><dt>Note</dt><dd>Method to read FUSE register in Direct Macro Access way. For reading the status values we need send the bitstream in shift DR state. Shift in MAGIC_CTS_WRITE "FEED28AC" for ultrascale Read 64 bit data in IR read state. </dd></dl>

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          <td class="memname">void JtagRead_Ultrascale </td>
          <td>(</td>
          <td class="paramtype">u8&#160;</td>
          <td class="paramname"><em>Row</em>, </td>
        </tr>
        <tr>
          <td class="paramkey"></td>
          <td></td>
          <td class="paramtype">u32 *&#160;</td>
          <td class="paramname"><em>RowData</em>, </td>
        </tr>
        <tr>
          <td class="paramkey"></td>
          <td></td>
          <td class="paramtype">u8&#160;</td>
          <td class="paramname"><em>MarginOption</em>, </td>
        </tr>
        <tr>
          <td class="paramkey"></td>
          <td></td>
          <td class="paramtype">u8&#160;</td>
          <td class="paramname"><em>Page</em>, </td>
        </tr>
        <tr>
          <td class="paramkey"></td>
          <td></td>
          <td class="paramtype">u8&#160;</td>
          <td class="paramname"><em>Redundant</em>&#160;</td>
        </tr>
        <tr>
          <td></td>
          <td>)</td>
          <td></td><td></td>
        </tr>
      </table>
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<p>This function reads entire row of Ultrascale's EFUSE. </p>
<dl class="params"><dt>Parameters</dt><dd>
  <table class="params">
    <tr><td class="paramname">Row</td><td>specifies the row number of EFUSE. </td></tr>
    <tr><td class="paramname">MarginOption</td><td>is a variable which tells the margin option in which read operation to be performed. </td></tr>
    <tr><td class="paramname">Page</td><td>tell the page of EFUSE in which the given row is located. </td></tr>
    <tr><td class="paramname">Redundant</td><td>is a flag to specify the bit to be programmed is Normal bit or Redundant bit.<ul>
<li>Redundant - XSK_EFUSEPL_REDUNDANT_ULTRA</li>
<li>Normal - XSK_EFUSEPL_NORMAL_ULTRA This variable is not valid for Ultrascale plus as each row contains both redundant and normal bits upper 16 are redundant.</li>
</ul>
</td></tr>
  </table>
  </dd>
</dl>
<dl class="section return"><dt>Returns</dt><dd>None.</dd></dl>
<dl class="section note"><dt>Note</dt><dd>Method to read FUSE register in Direct Macro Access way. Go to TLR to clear FUSE_CTS Load FUSE_CTS instruction on IR Step to CDR/SDR to shift in 32-bits FUSE_CTS command word Shift in MAGIC_CTS_WRITE "FEED28AC" for ultrascale Read 64 bit data in IR read state. </dd></dl>

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          <td class="memname">int JtagServerInit </td>
          <td>(</td>
          <td class="paramtype"><a class="el" href="struct_xil_s_key___e_pl.html">XilSKey_EPl</a> *&#160;</td>
          <td class="paramname"><em>PlInstancePtr</em></td><td>)</td>
          <td></td>
        </tr>
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<p>JTAG Server Initialization routine. </p>

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          <td class="memname">void JtagWrite </td>
          <td>(</td>
          <td class="paramtype">unsigned char&#160;</td>
          <td class="paramname"><em>row</em>, </td>
        </tr>
        <tr>
          <td class="paramkey"></td>
          <td></td>
          <td class="paramtype">unsigned char&#160;</td>
          <td class="paramname"><em>bit</em>&#160;</td>
        </tr>
        <tr>
          <td></td>
          <td>)</td>
          <td></td><td></td>
        </tr>
      </table>
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<p>JTAG Server Write routine. </p>

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          <td class="memname">int JtagWrite_Ultrascale </td>
          <td>(</td>
          <td class="paramtype">u8&#160;</td>
          <td class="paramname"><em>Row</em>, </td>
        </tr>
        <tr>
          <td class="paramkey"></td>
          <td></td>
          <td class="paramtype">u8&#160;</td>
          <td class="paramname"><em>Bit</em>, </td>
        </tr>
        <tr>
          <td class="paramkey"></td>
          <td></td>
          <td class="paramtype">u8&#160;</td>
          <td class="paramname"><em>Page</em>, </td>
        </tr>
        <tr>
          <td class="paramkey"></td>
          <td></td>
          <td class="paramtype">u8&#160;</td>
          <td class="paramname"><em>Redundant</em>&#160;</td>
        </tr>
        <tr>
          <td></td>
          <td>)</td>
          <td></td><td></td>
        </tr>
      </table>
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<p>This function blows the fuse of Ultrascale with provided parameters. </p>
<dl class="params"><dt>Parameters</dt><dd>
  <table class="params">
    <tr><td class="paramname">Row</td><td>specifies the row number of EFUSE to blow. </td></tr>
    <tr><td class="paramname">Bit</td><td>Specifies the bit location in the given row. </td></tr>
    <tr><td class="paramname">Page</td><td>tell the page of EFUSE in which the given row is located. </td></tr>
    <tr><td class="paramname">Redundant</td><td>is a flag to specify the bit to be programmed is Normal bit or Redundant bit.<ul>
<li>Redundant - XSK_EFUSEPL_REDUNDANT_ULTRA</li>
<li>Normal - XSK_EFUSEPL_NORMAL_ULTRA</li>
</ul>
</td></tr>
  </table>
  </dd>
</dl>
<dl class="section return"><dt>Returns</dt><dd>None.</dd></dl>
<dl class="section note"><dt>Note</dt><dd>None. </dd></dl>

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<h2 class="groupheader">Variable Documentation</h2>
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<p>Global variable which holds the error key. </p>

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<p>For Storing Fpga series. </p>

<p>Referenced by <a class="el" href="xilskey__jscmd_8c.html#a2240f1d411f1eef6605ee6da1426c5ba">JtagAES_Check_Ultrascale()</a>, <a class="el" href="xilskey__jscmd_8c.html#a2740a0531078952f78e0b2680f62cd1a">JtagRead_Ultrascale()</a>, and <a class="el" href="xilskey__jscmd_8c.html#ad71fe773dff0bd882d39c2936e319c63">JtagWrite_Ultrascale()</a>.</p>

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          <td class="memname">XilSKey_JtagSlr XilSKeyJtag</td>
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<p>JTAG Tap Instance. </p>

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